Stereo vision IP design for FPGA implementation of obstacle detection system
Systems, Signal Processing and their Applications（2013）
Abstract
Stereo vision IP (Intellectual Property) modules and obstacle detection systems using stereo vision is an important issue in intelligent vehicle, robots navigation and automotive. In this paper, we proposed an IP module with four (4) known stereo vision algorithms. The four algorithms architectures are compared in term of resources utilization and processing speed (frequency). We developed a software interface for VHDL code generation with needed IP parameters. The proposed IP-Based hardware architecture combines the stereo vision IP to compute the disparity map with V-disparity image and simplified Hough transform for obstacle detection. The proposed system was tested using Virtex-Il FPGA based prototyping board. Resources utilization and speed are estimated for different parameters of the disparity map algorithm.
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Key words
hough transforms,field programmable gate arrays,hardware description languages,stereo image processing,visual perception,fpga implementation,ip parameters,ip-based hardware architecture,v-disparity image,vhdl code generation,virtex-ii fpga based prototyping board,automotive,disparity map algorithm,intelligent vehicle,obstacle detection system,processing speed,resource utilization,robot navigation,simplified hough transform,software interface,stereo vision ip design,stereo vision intellectual property modules,computer architecture,stereo vision,algorithm design and analysis
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