Taper pad design to improve electrical performance of BGAs on wafer level package (WLP)
Electrical Design of Advanced Packaging and Systems Symposium（2012）
摘要
A taper pad design is proposed to improve signal integrity in the transition from traces on chip site to PCB. Transmission loss of the transition incorporating traces, taper pads, solder balls, and microstrip line is simulated through electromagnetic simulation tool. Compared with the conventional pad design, the proposed pad design has 2 dB of improvement and only 0.9 dB insertion loss at 40 GHz. In addition, its DC/AC parasitic resistance and AC parasitic inductance are extracted and proved to have 85/65 % and 19 % of reduction, respectively, against the conventional pad design. Finally, the design guide of the proposed pad design is presented to enhance the signal integrity of WLP.
更多查看译文
关键词
ball grid arrays,microstrip lines,printed circuits,wafer level packaging,ac parasitic inductance,bga,dc-ac parasitic resistance,pcb,wlp,electromagnetic simulation tool,frequency 40 ghz,loss 0.9 db,printed circuit boards,signal integrity,solder balls,taper pad design,transmission loss,wafer level package
AI 理解论文
溯源树
样例
生成溯源树，研究论文发展脉络
Chat Paper
正在生成论文摘要