An experimental high performance 16M DRAM using giga-bit technologies

An experimental high performance 16M DRAM having 0.18 ¿m design rule for giga bit DRAMs was developed. Junction leakage and junction capacitance was reduced by STI. Fast access time even at low operation voltage(~ 1.5V ) was achieved by TiSi2 gate, W-bit line, Ta2O5 capacitor, and new circuit techniques. Insufficient depth of focus margin for Back-End of Line process was overcome by triple metallization scheme with one W and two Al metals. Owing to these, high speed (Trac= 28 ns at 1.5V ) and small chip size(5.3×5.4 mm2) was achieved.