A Wideband CMOS Noise-Canceling Low-Noise Amplifier With High Linearity

This letter presents a wideband noise-canceling LNA focusing on canceling IMD2 and IMD3. By using a complementary CMOS parallel push-pull structure, the IMD2 is cancelled. The modified noise-canceling circuit properly suppresses the IMD3. Although the optimum canceling points for the noise and distortions are different, the noise figure is not degraded by the choice. The LNA implemented in a 65 nm CMOS process delivers an IIP2 of 25 dBm, an IIP3 of 5.5 dBm with a power gain of 13 dB and an noise figure of 2.1–3.5 dB in a frequency range from 0.1 to 1.6 GHz. The power consumption is 20.8 mW at 1.2 V and the chip area is only .