Impact of parameter variations on FinFET faults

The technology shrinking strategy below 20nm feature sizes adopted by the giants of the nowadays semiconductor industry has boosted the research on FinFET which is considered as an alternative to the conventional planar technology. This paper presents a comprehensive study carried out for FinFET-based memories using an advanced flow for fault modeling and test algorithm generation. Using this flow it has been shown that parameter variation (of process, voltage, temperature, frequency) has a significant impact on the fault coverage when dealing with FinFET-specific faults.