A scalable hardware architecture for retinal blood vessel detection in high resolution fundus images

Blood vessel detection from high resolution fundus images is a necessary step in several medical applications. Automatic blood vessels detection is a computing intensive task which raises the need for accelerated hardware architectures. In this paper, we propose a scalable hardware architecture for blood vessel detection using a matched filter (MF). The algorithm is made hardware friendly using parallel processing and efficient resources sharing to achieve real-time performances. The paper also introduces a tool for the automatic generation of an HDL description based on the proposed architecture as a template. The tool takes as input the parameters of the filter to deal with the parameter selection problem and to make their choice more flexible. Performances in terms of area utilization and maximum frequency are reported. Several designs were verified and implemented on an FPGA platform. The results show significant improvements over the state of the art implementations, up to a factor of 10× for high resolution fundus images.