Synchronization concept for the characterization of integrated circuits with multi-gigabit receivers and a slow feedback channel
Microwave Conference（2015）
Abstract
This paper presents an off-line synchronization concept for the characterization of integrated circuits with receivers operating in the Gb/s range. The concept relies on the use of a programmable FPGA board with fast transmitters, a configurable delay board and an undersampling test register at the receiver side.
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Key words
circuit feedback,delays,field programmable gate arrays,receivers,synchronisation,channels maximum relative delay,configurable delay board,integrated circuits characterization,multigigabit receivers,off-line synchronization concept,programmable fpga board,slow feedback channel,undersampling test register
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