On the thermal performance analysis of three-dimensional chip stacking electronic packaging with through silicon vias
Electronic Packaging and iMAPS All Asia Conference（2015）
摘要
The study aims at investigating the thermal performance of a quad-flat (QF) type three-dimensional (3D) through silicon vias (TSV) IC package on board in a steady state under natural convection based on JEDEC standards, and furthermore, conducting thermal management. A 3D heat conduction finite element model (FEM) incorporating an FEM-based averaging technique and a rule of mixture (ROM) method for developing an equivalent thermal model for the TSV chip and circuited substrate/test board is proposed. The predicted effective thermal conductivities are compared with each other. In addition, their dependences on some key design parameters are examined. The calculated results are compared against three thermal measurement data. Besides, the uncertainties in the input chip power from the specific power supply and in the measured chip junction temperature by the thermal test die measurement are also assessed.
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关键词
finite element analysis,heat conduction,integrated circuit modelling,integrated circuit packaging,natural convection,thermal conductivity,thermal management (packaging),three-dimensional integrated circuits,3d heat conduction fem,3d heat conduction finite element model,fem-based averaging technique,jedec standards,qf-type 3d ic package,tsv chip,circuited substrate-test board,equivalent thermal model,measured chip junction temperature,predicted effective thermal conductivity,quad-flat type three-dimensional through silicon vias ic package,rule-of-mixture method,thermal management,thermal measurement data,thermal test die measurement,three-dimensional chip stacking electronic packaging,through silicon vias,3d tsv ic,fe modeling,ir thermometer,t3ster,thermal test die,uncertainty analysis,temperature measurement,uncertainty,conductivity
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