Process integration and 3D chip stacking for low cost backside illuminated CMOS image sensor

Hsianghung Chang,Zhicheng Hsiao,Jenchun Wang,Chunhsien Chien,Chengta Ko,Chaujie Zhan,Yuwei Huang,Yuchen Hsin,Chungchih Wang,Peijer Tzeng,Chahsin Lin,Chiahsin Lee,Tingsheng Chen,Weichung Lo,Tzukun Ku,Yungfa Chou,Dingming Kwai,Mingjer Kao

VLSI Technology, Systems and Application（2015）

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摘要

A novel low cost backside illuminated CMOS image sensor structure is proposed in this research. By using thin wafer handling technology, the wafer is thinned down to less than 5 μm and no TSV and direct bonding process are needed in this low cost solution. The processed backside illuminated CMOS image sensor is then stacked with analog to digital conversion chip and image signal processor by 3DIC technology. A 3-Mega pixel image is captured and demonstrated in this research.

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关键词

tsv,process integration,dry etching,through silicon via,stacking

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