FPGA implementation of JPEG-LS compression algorithm for real time applications
Electrical Engineering（2011）
摘要
Summary from only given. This paper presents some propositions to reduce consuming memory and increase operational frequency of hardware implementation of JPEG-LS algorithm for real time applications. By enhancement in the algorithm and using fast divider, memory has been reduced by 24%. Also, considering the proposed non-stalling pipeline architecture by using forwarding technique to avoid hazards, circuit frequency has increased to 155.2MHz and any 512×512 pixel image can be compressed in less than 1700us at these frequency and architecture. Compressor architecture was described by VerilogHDL and implemented on ALTERA Stratix II FPGA.
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关键词
veriloghdl,jpeg-ls,image coding,memory,hardware implementation,hardware description languages,pipeline,fpga,data compression,fast divider,forwarding,operational frequency,jpeg-ls compression algorithm,compressor architecture,field programmable gate arrays,forwarding technique,real-time systems,real time applications,altera stratix ii fpga,pipeline processing,mathematical model,hardware,pipelines,compression algorithm,real time systems,pixel
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