A highly manufacturable integration technology for 27nm 2 and 3bit/cell NAND flash memory

Choongho Lee,Sukkang Sung,D Jang,Sehoon Lee,Seungwook Choi,Jonghyuk Kim,Sejun Park,Minsung Song, Hyunchul Baek,Eungjin Ahn,Jinhyun Shin,Kwangshik Shin, Kyunghoon Min, Sungsoon Cho,Changjin Kang,Keonsoo Kim,Jeonghyuk Choi,Kangdeog Suh,Taesung Jung

Electron Devices Meeting（2010）

Cited 25|Views33

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Abstract

A highly manufacturable multi-level NAND flash memory with a 27nm design rule has been successfully developed for the first time. Its unit cell size is 0.00375um2 (with overhead). Self Aligned Reverse Patterning is used to improve initial Vth distribution induced from DPT (Double Patterning Technology) process. By using advanced channel doping technique, the channel junction leakage is minimized and the Vpass window is improved. The optimized doping structure and cell operation scheme are evaluated. And finally 2 and 3bit per cell operation are successfully demonstrated with flash cells of 32Gb density with reasonable reliability.

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Key words

nand circuits,flash memories,logic design,nand flash memory,channel doping technique,channel junction leakage,double patterning technology,integration technology,self aligned reverse patterning,wavelength 27 nm,doping,design rules,oxidation,computer architecture,reliability,logic gates

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