Methodology for early and accurate test power estimation at RTL
Test Conference(2010)
Abstract
Test power consumption impacts various aspects of an SOC design cycle ranging from packaging and power grid design to tester power supply requirements. Obtaining early and accurate test power estimates has so far been a bottleneck since design-for-test (DFT) modifications such as scan manifest only in the gate-level circuit representation. In this work, we describe a methodology that enables us to perform early and efficient power estimation for scan-based circuits at RTL. We explain the method, its realization using features of a commercial power estimation engine and its evaluation on various production 65nm and 45nm industrial designs.
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Key words
boundary scan testing,design for testability,integrated circuit design,system-on-chip,DFT modifications,RTL,SOC design cycle,commercial power estimation engine,design-for-test modifications,gate-level circuit representation,packaging,power grid design,scan-based circuits,test power consumption,test power estimates,test power estimation,tester power supply requirements
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