Characterization of TSV-Induced Loss and Substrate Noise Coupling in Advanced Three-Dimensional CMOS SOI Technology
Components, Packaging and Manufacturing Technology, IEEE Transactions(2013)
摘要
Electrical loss and substrate noise coupling induced by through-silicon-vias (TSVs) in silicon-on-insulator (SOI) substrates is characterized in frequency and time domains. A three-dimensional (3-D) test site in 45-nm CMOS SOI including copper-filled TSVs and microbumps ( μC4's) is fabricated and measured to extract the interconnect loss. Good correlation to the electrical circuit models is demonstrated up to 40 GHz. In addition to a buried oxide layer, a highly doped N+ epilayer used for deep trench devices in 22-nm CMOS SOI is considered in full-wave electromagnetic simulations. Equivalent circuit models are extracted to assess the impact of noise coupling on active circuit performance. A noise mitigation technique of using CMOS process compatible buried interface contacts is proposed and studied. Simulation results demonstrate that a low-impedance ground return path can be readily created for effective substrate noise reduction in 3-D IC design.
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关键词
cmos integrated circuits,buried layers,equivalent circuits,integrated circuit design,integrated circuit interconnections,integrated circuit noise,semiconductor epitaxial layers,silicon-on-insulator,three-dimensional integrated circuits,time-frequency analysis,3d ic design,n+ epilayer,soi substrates,si,tsv-induced loss,active circuit performance,buried interface contact,buried oxide layer,copper-filled tsv,deep trench device,electrical circuit model,electrical loss,equivalent circuit model,frequency-time domains,full wave electromagnetic simulation,low impedance ground return path,noise mitigation technique,silicon-on-insulator substrates,size 22 nm,size 45 nm,substrate noise coupling,three-dimensional cmos soi technology,three-dimensional test site,through-silicon-via technology,3-d integrated circuit (ic),3-d integration,on-chip interconnect,signal integrity,substrate noise,through-silicon-via (tsv),time frequency analysis,silicon on insulator
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