EDA software for verification of metal interconnects in ESD protection networks at chip, block, and cell level

Maxim Ershov,Yuri Feinberg,Meruzhan Cadjan,David Klein,Melanie Etherton

Electrical Overstress/Electrostatic Discharge Symposium（2013）

Cited 27|Views4

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Abstract

A new EDA tool suite is presented for layout verification of ESD protection networks. It uses novel methodologies to accurately analyze interconnect resistance and current density, enabling quick identification of ESD weak areas at chip, block and detailed cell levels. The suite also includes a precision capacitance extraction tool.

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Key words

current density,electronic design automation,integrated circuit interconnections,eda software,eda tool suite,esd protection networks,esd weak areas,block level,cell level,chip level,interconnect resistance,layout verification,metal interconnects,precision capacitance extraction tool

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