Two-channel receiver back-end using statistically calibrated HRM with >70dB 3rd and 5th harmonic rejection for carrier aggregation in 32nm CMOS
VLSI Circuits（2013）
摘要
A wideband receiver back-end supporting dual band reception for carrier aggregation has been implemented in 32nm CMOS. The proposed architecture relies on tunable phase generation circuitries, feeding parallel paths consisting of a harmonic rejection mixer and a ΔΣ-ADC. 3rd and 5th order harmonic distortion is suppressed through statistical calibration, exploiting the inherent circuit variability, achieving HR3 and HR5 jointly exceeding 70dB when tested across multiple dies, while dissipating 16mW per back-end channel and covering a mixing range of 240MHz.
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关键词
CMOS integrated circuits,analogue-digital conversion,mixers (circuits),radio receivers,statistical analysis,ΔΣ-ADC,CMOS,carrier aggregation,dual band reception,harmonic rejection mixer,statistically calibrated HRM,two-channel receiver,wideband receiver,Carrier Aggregation and Statistical Calibration,Harmonic Rejection,
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