Dielectric stack engineering for via-reveal passivation

Kath Crook,Mark Carruthers,Daniel Archard,Steve Burgess,Keith Buchanan

Electronic Components and Technology Conference（2013）

引用 13|浏览5

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摘要

This paper reports on the development of low temperature (<;190°C) plasma-enhanced chemical vapour deposition (PECVD) processes used to deposit dielectric films for use as passivation layers over wafer back side revealed vias in thinned (<;60μm), 300mm silicon wafers.

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关键词

dielectric thin films,passivation,plasma cvd,three-dimensional integrated circuits,wafer-scale integration,pecvd process,si,tsv,dielectric film deposition,dielectric stack engineering,passivation layers,plasma-enhanced chemical vapour deposition process,silicon wafers,size 300 mm,via-reveal passivation,wafer back side,films,silicon,tensile stress,temperature measurement

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