System Scaling and Collaborative Open Innovation
Symposium on VLSI Technology（2013）
关键词
CMOS integrated circuits,copper,energy conservation,integrated circuit interconnections,low-k dielectric thin films,low-power electronics,nanoelectronics,silicon,three-dimensional integrated circuits,transistor circuits,CMOS processor,Cu,Moore law,Si,TSV 3D chip stacking,collaborative open innovation,copper through-Si-via,density scaling,energy efficiency,energy-efficient scaling,energy-efficient transistor,form factor reduction,giga trends,high-density transistor,information throughput,integration density,low supply voltage,low-k on-chip interconnect,memories,mobile computing,nanoelectronics industry,parallelism,power saving,processor core,silicon wafer-based chip scaling,system component,system integration platform,system partitioning,system requirements,system scaling,3DIC,CMOS,VLSI,computing power,scaling,system optimization
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