Investigation of 1T DRAM cell with non-overlap structure and recessed channel

Sang Wan Kim,Garam Kim,Wonjoo Kim,Hyoungsoo Ko,Byunggook Park

Silicon Nanoelectronics Workshop（2010）

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摘要

In this paper, a capacitor-less 1T DRAM cell transistor with non-overlap structure and recessed channel is presented. Because of the non-overlap structure between gate and source/drain, GIDL (Gate Induced Drain Leakage) current is efficiently suppressed at hold condition. This results in more than 1 s retention time at 25°C and 100 ms at 85°C.

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关键词

dram chips,capacitorless 1t dram cell transistor,gate induced drain leakage current,non-overlap structure,recessed channel,temperature 25 degc,temperature 85 degc,time 1 s,retention time,logic gates,sensors,transistors,electric potential,simulation

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