A 5Gb/s link with clock edge matching and embedded common mode clock for low power interfaces
VLSI Circuits(2010)
摘要
A 5Gb/s signaling system was designed and fabricated in TSMC's 40nm LP CMOS process. A new clock/data skew minimization technique with a source-synchronous transmit clock delay line and integrating receiver tolerates high frequency transmit clock jitter and supports rapid turn-on without the clock buffer latency of conventional source-synchronous systems. A second method to minimize clock distribution via embedded clocking with superposition of clock in the common-mode was also explored.
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关键词
I/O,low-power,source-synchronous clocking,integrating receiver,common-mode clocking,jitter tracking
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