A 5Gb/s automatic sub-bit between-pair skew compensator for parallel data communications in 0.13µm CMOS
VLSI Circuits（2010）
摘要
A between-pair skew compensator for parallel data communications is presented. It can detect time skew between two independent data sequences using continuous-time correlations and then automatically align the two using a voltage controlled wide-bandwidth data delay line. A 5Gb/s sub-bit between-pair skew compensator in 0.13μm CMOS occupies 0.03mm2 active die area and dissipates 22.5mW.
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关键词
cmos integrated circuits,data communication,parallel processing,cmos process,automatic sub-bit between-pair skew compensator,bit rate 5 gbit/s,continuous-time correlation,data sequence,parallel data communication,power 22.5 mw,size 0.13 mum,time skew detection,voltage controlled wide-bandwidth data delay line,logic gates,detectors
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