Modified FPGA based design and implementation of reconfigurable FFT architecture
Automation, Computing, Communication, Control and Compressed Sensing（2013）
摘要
Fast Fourier Transforms, popularly known as FFTs, have become an integral part of any digital communication system and a wide variety of approaches have been tried in order to optimize the algorithm for a variety of parameters, primarily Area, Memory and Speed. The aim is to build a Reconfigurable Fast Fourier Transform Block which is suitable for any signal processing application, especially for communication blocks such as OFDM receivers. The objective is to design an FFT block that is capable of computing any N-point FFT and employs R2SDF (Radix 2 Single Delay Feedback) architecture with a single ROM. The design has been developed using the hardware description language VHDL on Xilinx xc5vlx110t. The result shows significant reduction in area for this architecture.
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关键词
ofdm modulation,digital arithmetic,digital communication,fast fourier transforms,field programmable gate arrays,hardware description languages,logic design,read-only storage,reconfigurable architectures,signal processing,fft block,fpga based design,n-point fft,ofdm receivers,r2sdf,vhdl,xilinx xc5vlx110t,communication blocks,digital communication system,hardware description language,radix 2 single delay feedback architecture,reconfigurable fft architecture,reconfigurable fast fourier transform block,single rom,fast fourier transform,r2spdf,single path delay feedback,single rom architecture,computer architecture,algorithm design and analysis,read only memory
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