A low-power 6.6-Gb/s wireline transceiver for low-cost FPGAs in 28nm CMOS

Jafar Savoj,Kenny Hsieh,Futai An,Michael Buckley,Jay Im,Xuewen Jiang,Anup P Jose,Vassili Kireev,Kang Wei Lai, Hiep Pham,Didem Turker,Dan Wu,Ken Chang

Solid State Circuits Conference（2012）

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摘要

This paper describes the design of a 0.5-6.6Gb/s fully-adaptive low-power quad transceiver embedded in state-of-the-art low-leakage 28nm CMOS FPGAs. The receiver front-end utilizes a wide input common-mode circuit and a 3-stage CTLE to remove the immediate post-cursor ISI. The CTLE is fully adaptive using sign-sign LMS algorithm and edge-based equalization. The transmitter utilizes a 3-tap FIR. The clocking network provides continuous operation range up to the maximum speed and incorporates two wide-range ring-based PLLs for enhanced clocking flexibility. The transceiver achieves BER <; 10-15 at 6.6Gb/s over an 18dB loss channel. Power consumption is 129mW from 1.2V and 1V supplies.

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关键词

cmos logic circuits,fir filters,equalisers,field programmable gate arrays,interference suppression,intersymbol interference,least mean squares methods,low-power electronics,phase locked loops,transceivers,3-stage ctle,3-tap fir,bit rate 6.6 gbit/s,clocking network,common-mode circuit,edge-based equalization,fully-adaptive low-power quad transceiver,immediate post-cursor isi,loss 18 db,low-cost fpga,low-leakage cmos fpga,low-power wireline transceiver,power 129 mw,receiver front-end,sign-sign lms algorithm,size 28 nm,transmitter,voltage 1 v,voltage 1.2 v,wide-range ring-based pll,low power electronics

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