Reliability Studies on a 45nm Low Power System-on-chip (soc) Dual Gate Oxide High-K / Metal Gate (DG HK+MG) Technology
IEEE International Reliability Physics Symposium（2010）
Key words
electric breakdown,high-k dielectric thin films,integrated circuit reliability,logic circuits,system-on-chip,transistors,BTI,DG HK+MG technology,HCI degradation,HVM reliability,I/O transistors,SoC,TDDB degradation,dual gate oxide high-k/metal gate technology,logic transistors reliability,low power system-on-chip,process optimization,size 45 nm,time dependent dielectric breakdown
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