10-Gb/s BM-CDR Circuit With Synchronous Data Output for Optical Networks

This letter presents a 10-Gb/s burst-mode clock and data recovery (BM-CDR) circuit based on an analog phase-picking method. The experiment demonstrates that the proposed BM-CDR circuit is able to align the BM data to a local clock with a phase alignment accuracy of ±π/4, a 25-ns latency and zero bit loss. The circuit further resamples the aligned data using the local clock for jitter reduction. The experiment shows error-free operation of the BM-CDR circuit for burst-mode data packets with various phase delays.