A noise reduction technique for wideband LNAs in low-power digital TV applications
Electrical Engineering（2012）
摘要
A low power ultra wideband very low noise amplifier is presented. The proposed LNA scheme uses two parallel nMOS and pMOS cascode common gate (CG) branches, an active positive feedback and input matching extender. Compared to the CG structure, the proposed LNA results in improved noise figure and input matching over a wide bandwidth with the same power consumption. Circuit level analysis and simulation results are provided to verify the effectiveness of the proposed LNA scheme. Simulated in a 0.18μm RF CMOS technology, the proposed LNA achieves a noise figure of 2.2 to 2.5 dB and input return loss (S11) less than -10 dB over whole bandwidth while consumes only 2.7 mW power from a 1.8 V power supply. The -3 dB power gain (S21) is 19.7 dB and maximum values of IIP3 and IIP2 are -6 dBm and 15 dBm, respectively.
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关键词
CMOS analogue integrated circuits,circuit simulation,digital television,feedback amplifiers,low noise amplifiers,low-power electronics,wideband amplifiers,CG structure,RF CMOS technology,active positive feedback,circuit level analysis,circuit level simulation,gain -3 dB,gain 19.7 dB,input matching extender,input return loss,low power ultra wideband very low noise amplifier,low-power digital TV application,noise figure,noise figure 2.2 dB to 2.5 dB,noise reduction technique,pMOS cascode common gate branch,parallel nMOS branch,power 2.7 mW,power consumption,size 0.18 mum,voltage 1.8 V,wideband LNA,
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