Design of a low power 10-bit cyclic D/A converter with a Johnson counter and a capacitor swapping technique
Toulouse(2009)
Abstract
A cyclic 10-bit D/A converter based on a Johnson counter and a capacitor swapping technique is described. To reduce capacitor mismatching errors, two capacitors are alternately swapped according to input data. Further, a half differential architecture to reduce offset errors and a Johnson counter to improve the digital logic performance are proposed. With a 0.35 mum Samsung CMOS technology, the measured SFDR is about 65 dB, when the input frequency is 1 MHz at a clock frequency of 2 MHz. The power consumption is only 310 muW at 3.3 V power supply. The measured INL and DNL are within plusmn0.7 LSB and plusmn0.75 LSB, respectively.
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Key words
cmos logic circuits,capacitors,clocks,counting circuits,digital-analogue conversion,low-power electronics,johnson counter,samsung cmos technology,capacitor mismatching errors,capacitor swapping,clock frequency,digital logic,frequency 1 mhz,frequency 2 mhz,low power cyclic d/a converter,power 310 muw,size 0.35 mum,voltage 3.3 v,cmos integrated circuits,low power electronics,switches
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