Advanced flip-chip package solution for 28nm Si node and beyond

C S Liu,C S Chen,C H Lee,H Y Tsai,H P Pu,M D Cheng, T H Kuo, H W Chen,C Y Wu,M J Lii,Doug C H Yu

Electronic Components and Technology Conference（2012）

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摘要

Next generation flip chip package with <;100um fine bump pitch is developed in a cost effective Bump-on-Trace (BOT) package structure for 28nm Si technology node. This is foreseen to be a mainstream for mobile applications in next generations. The key challenges of this new technology include warpage control of molded underfill (MUF) for <; 4 mils of thin die, packaging yield due to finer pitch of bumping/substrate design and thermal/mechanical effect on chip-package-interaction (CPI) [1-2]. CPI due to the use of fragile extreme low-k (ELK) dielectric material in the back-end-of-line (BEOL) layers has been fully characterized. The well-integrated Si/bump/package processes enable reliable CPI and assembly yield. An aggressive and reliable Si/bump/package design and CPI approaches are also discussed.

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关键词

elemental semiconductors,flip-chip devices,low-k dielectric thin films,reliability,silicon,beol layers,bot package structure,cpi reliability,muf,si,advanced flip-chip package solution,back-end-of-line layers,bump pitch,bump-on-trace package structure,bumping-substrate design,chip-package-interaction,fragile elk dielectric material,fragile extreme low-k material,mobile applications,molded underfill,next generation flip chip package,size 28 nm,thermal-mechanical effect,warpage control,flip chip,assembly,stress

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