Concurrent L- and S-band class-E power amplifier in 65nm CMOS

Ronghui Zhang,Acar, M.,Apostolidou, M.,van der Heijden, M.P.

Radio Frequency Integrated Circuits Symposium（2012）

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Abstract

A 65nm CMOS concurrent dual-band two-stage class-E power amplifier (PA) using high voltage extended-drain devices is presented. To implement sub-optimum class-E load impedance at L-band (1.0-1.3GHz) and S-band (2.8-3.1GHz), a concurrent transmission-line based dual-band output matching network is designed. The measurements show a drain efficiency (η) >; 61% and a power-added efficiency (PAE) >; 50.5% for L-band (1.0-1.3GHz) with a output power Pout >; 30.4dBm. For S-band (2.8-3.1GHz) a η >; 42.6% and a PAE >; 30% with a Pout >; 28.9dBm are achieved. The output power variations are within 0.8dB and 1.6dB, respectively.

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Key words

CMOS analogue integrated circuits,UHF power amplifiers,nanoelectronics,CMOS,CMOS concurrent dual-band two-stage class-E power amplifier,L-band class-E power amplifier,S-band class-E power amplifier,class-E load impedance,concurrent transmission-line based dual-band output matching network,drain efficiency,frequency 1 GHz to 3.1 GHz,high voltage extended-drain device,power-added efficiency,size 65 nm,CMOS power amplifier,Class-E,Dual-band,

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