A Dual-Channel 10b 80ms/S Pipeline Adc With 0.16mm(2) Area In 65nm Cmos

Xinyu Yu,Fang Lin,K Li,Sumant Ranganathan,Tom Kwan

Kyoto, Japan（2009）

引用 24|浏览2

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摘要

A dual-channel 10b 80MS/s low-power and area-efficient pipeline ADC is presented. Area and power savings are realized by merging the track and hold amplifier (THA) and the 1(st)-stage multiplying digital-to-analog converter (MDAC), double-sampling the 2(nd)-stage MDAC and using a 1b sub-range in 4b sub-ADC. It achieves an ENOB of 8.65b with 20.1-MHz input. Including on-chip reference buffers, power and area consumption are 11.2mW and 0.08mm(2) per channel respectively.

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关键词

capacitance,chip,merging,noise,capacitors,cmos integrated circuits,sampling methods,very large scale integration,throughput,data mining,pipelines,switches

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