A 2.0 to 3.0 GHz CMOS low noise amplifier and its applications
Engineering（2011）
摘要
This paper presents a 2 GHz to 3 GHz Low Noise Amplifier (LNA) design based on a cascode topology. The proposed method is addressed to optimize noise performance and power efficiency while maintaining good input and output matching. This LNA has a measured power gain of 13.5dB and noise figure of 1.5 dB. The output insertion loss S22 is -9dB. input return loss (s11) is -22dB. The design simulation process is using Advance Design System (ADS) software and implemented in TSMC 0.18 μm CMOS technology with very low power dissipation.
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关键词
CMOS analogue integrated circuits,UHF amplifiers,low noise amplifiers,microwave amplifiers,network topology,ADS software,CMOS LNA,CMOS low noise amplifier,TSMC CMOS technology,advance design system software,cascode topology,design simulation process,frequency 2.0 GHz to 3.0 GHz,gain 1.5 dB,input return loss,loss -22 dB,optimize noise performance,output insertion loss,power dissipation,power efficiency,Advanced Design System,CMOS Low noise amplifier,RFIC Design,VLSI,
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