A 1.8V 200mW 8-bit 1GSPS CMOS A/D converter with a cascaded-folding and an interpolation
Austin, TX(2009)
Abstract
In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 1GSPS at 1.8 V is designed. The architecture of the proposed ADC is based on a folding ADC with a cascaded-folding and an interpolation structure. A self-linearized pre-amplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18 mum 1-poly 5-metal CMOS technology. The active chip area is 0.72 mm2 and it consumes about 200 mW at 1.8 V power supply. The simulated result of SNDR is 46.29 dB, when Fin=Fs/2 at Fs=1 GHz.
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Key words
cmos integrated circuits,analogue-digital conversion,encoding,interpolation,1-poly 5-metal cmos technology,8-bit 1gsps cmos a/d converter,analog-to-digital converter,auto-switching encoder,cascaded-folding,folder averaging technique,frequency 1 ghz,noise figure 46.29 db,power 200 mw,self-linearized preamplifier,size 0.18 mum,source degeneration technique,voltage 1.8 v,word length 8 bit,adc,folder averaging,digital signal processing,error correction,moon,linearity,resistors,phase locked loops,jitter,chip,cmos technology,voltage
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