75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques.

Rex Kho, David Boursin,Martin Brox,Peter Gregorius,Heinz Hoenigschmid,Bianka Kho, Sabine Kieser,Daniel Kehrer,Maksim Kuzmenka,Udo Moeller, Pavel Veselinov Petkov,Manfred Plan,Michael Richter,Ian Russell,Kai Schiller,Ronny Schneider,Kartik Swaminathan,Bradley Weber,Julien Weber,Ingo Bormann,Fabien Funfrock, Mario Gjukic,Wolfgang Spirkl,Holger Steffens,Jörg Weller,Thomas Hein

San Francisco, CA（2009）

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摘要

In this paper, a 7 Gb/s/pin 1 Gb GDDR5 DRAM with an array architecture for fast column access, a boosting transmitter, multiple voltage (V|NT) domains to control on chip power noise, and a high-speed internal VINT power generator system are presented. This 1Gb GDDR5 memory device is fabricated in a conventional 75 nm DRAM process and characterized for a 7Gb/s/pin data transfer rate at 1.5 V. To achieve fast column-column access times, array improvements are necessary.

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关键词

DRAM chips,integrated circuit design,integrated circuit noise,DRAM,GDDR5 graphic memory device,bandwidth-improvement technique,bit rate 7 Gbit/s,boosting transmitter,data transfer rate,master column-select lines,multiple voltage domain,on chip power noise,power generator system,size 75 nm,

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