On Implementation Of Embedded Phosphorus-Doped Sic Stressors In Soi Nmosfets

We report a successful implementation of epitaxially grown Phosphorus-doped (P-doped) embedded SiC stressors into SOI nMOSFETs. We identify a process integration scheme that best preserves the SiC strain and minimizes parasitic resistance. At a substitutional C concentration (C-sub) of similar to 1.0%, high performance nFETs with SiC stressors demonstrate similar to 9% enhanced I-eff and similar to 15% improved I-dlm against the well calibrated control devices. It is found that the tensile liner technique provides further performance improvement for nFETs with SiC stressors, whereas the Stress Memory Technique (SMT) does not provide performance gain in a laser annealing process that is used to preserve SiC strain. The material quality of the SiC stressors strongly affects stain transfer.