Post breakdown oxide lifetime based on digital circuit failure

The Reliability margin of aggressively scaled SiO-based gate dielectrics is strongly reduced. However, the first breakdown (BD) event of ultrathin oxide MOS devices does not always cause the functional failure of digital circuits. This opens the possibility of gaining additional reliability margins from the post-BD stage and has motivated a lot of research in this field. One of the areas of activity has been the study of the statistics of successive BD events because a very important chip lifetime enhancement is obtained when a number of BD events are tolerated without chip failure. However the lifetime extension based on basic transistor parameters shift DeltaVt, DeltaIdsat after breakdown is lacking. This paper provides the first methodology which extends the lifetime of a broken transistor using typical transistor failure criteria: DeltaVt = 50 mV and DeltaIdsat = 10%. The lifetime extension provided by this new methodology is compared to lifetime extension based on multiple breakdowns on a same device and on the chip.