Development of 38nm Bit-Lines Using Copper Damascene Process for 64-Giga Bits Nand Flash

Byungjoon Hwang,Namsu Lim,Jang-Ho Park,Sowi Jin, Minjeong Kim,Jaesuk Jung,Byungho Kwon,Jongwon Hong,Jeehoon Han,Donghwa Kwak,Jaekwan Park,Jung-Dal Choi,Won-Seong Lee

2008 IEEE/SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE（2008）

Cited 9|Views2

Key words

NAND circuits,buffer circuits,copper,flash memories,NAND flash,buffer forces,cell strings,copper damascene process,parasitic capacitance,parasitic capacitance suppression,self-aligned double patterning process,sheet resistance

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