Effect of Buffer Layer on Single-Event Burnout of Power DMOSFETs

It has been shown, both experimentally and theoretically, that the addition of a buffer layer between the epitaxial layer and substrate can improve a device's single event burnout (SEB) survivability. Simulation results show that the choice of buffer, resistivity and thickness, is important in achieving the best device performance (i.e., to fabricate a device capable of withstanding a heavy ion environment under its full rated drain voltage without a significant increase in its on-resistance). Simulation results show that an optimized buffer layer is critical. In other words, if the resistivity is too low or high and/or the thickness is too thick or thin, the drain voltage at which SEB occurs decreases. This paper provides a methodology to select an optimized buffer layer resistivity and thickness.