Performance and Yield Optimization of mm-Wave PLL Front-End in 65nm SOI CMOS

Daihyun Lim,Jonghae Kim,J O Plouchart,Daeik Kim,Choongyeun Cho,Duane S Boning

Radio Frequency Integrated Circuits（2007）

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摘要

A combination of LC-VCO and 2:1 CML static frequency divider has been fabricated in 65 nm SOI CMOS technology and operates at 70 GHz. A cascoded buffer amplifier is used in VCO-to-divider connection to compensate for the power losses caused by interconnect parasitics, and inductive peaking is employed for bandwidth enhancement. The bias condition of the frequency divider has been tuned to find an optimal bias point in existence of VCO and frequency divider operating range variation. The inter-die variation of VCO and divider performance variations over a wafer and their correlation have been estimated.

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关键词

cmos integrated circuits,circuit optimisation,circuit tuning,compensation,current-mode logic,frequency dividers,integrated circuit yield,millimetre wave amplifiers,millimetre wave integrated circuits,millimetre wave oscillators,phase locked loops,voltage-controlled oscillators,cml static frequency divider,lc-vco,soi cmos,bandwidth enhancement,bias condition tuning,cascoded buffer amplifier,frequency 70 ghz,inductive peaking,inter-die variation,interconnect parasitics,mm-wave pll front-end,power loss compensation,size 65 nm,yield optimization,process variation,vco,frequency divider,mm wave cmos,parasitic capacitance,tuning,cmos technology,front end

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