Development and Use of Small Addressable Arrays for Process Window Monitoring in 65nm Manufacturing

Madurakavi Karthikeyan,Arthur Gasasira, Sarah A Fox,Greg Yeric,Mathew Hall

Tokyo（2007）

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摘要

In this paper we report on the development and use of two scribe-line compatible addressable array test structures in 65 nm technology for routine process window monitoring. One array was dedicated for front-end of line test structures, while a second consists exclusively of back-end test structures. Fast testing allows large-scale sampling of wafer lots in a manufacturing environment. Customized software is used to automate data analysis and calculate figures of merit that enable process and equipment performance to be tracked by process module. Examples of successful application of these arrays in identifying and addressing systematic yield detractors are provided.

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关键词

arrays,integrated circuit design,integrated circuit manufacture,integrated circuit technology,integrated circuit testing,integrated circuit yield,large scale integration,process monitoring,automate data analysis,back-end test structures,customized software,figures of merit calculation,front-end test structures,large-scale sampling,process window monitoring,scribe-line compatible addressable array test structures,semiconductor defects,semiconductor device manufacturing environment,size 65 nm,systematic yield detractors,yield optimization,semiconductor device manufacture,semiconductor devices,figure of merit,system testing,microelectronics,data analysis,front end,read only memory

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