A Low Power and High Performance SOI SRAM Circuit Design with Improved Cell Stability

Rajiv V Joshi, Yijen Chan,Donald W Plass,Timothy J Charest, Ryan Freese,R Sautter,William V Huott,Uthara Srinivasan,Daniel Rodko, P Patel,Philip G Shephard,Tobias Werner

Niagara Falls, NY（2006）

Cited 13|Views48

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Abstract

An embedded CMOS static random access memory (SRAM), including the array and a method of accessing cells in the array with improved cell stability for scalability and performance (over 5 GHz) is demonstrated in hardware using 65 nm partially depleted silicon on insulator (PD SOI) technology. The design features shorter bitlines (16 cells/bitline) along with a thin cell layout and programmable domino read operation. Bit lines connected to half selected cells in the array are floated during cell accesses for improved cell stability. In addition, the SRAM is supplied with multiple supplies: one to the cells, wordline drivers, and level shifters, and the other to the bitline and remaining logic to improve stability and lower power

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Key words

cmos memory circuits,sram chips,low-power electronics,nanoelectronics,programmable circuits,silicon-on-insulator,65 nm,cmos static random access memory,soi sram circuit,si,cell accesses,improved cell stability,low power sram,partially depleted silicon on insulator,programmable domino read operation,thin cell layout,static random access memory,low power electronics,circuit design,silicon on insulator

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