X-MatchPRO: A High Performance Full-Duplex Lossless Data Compressor on a ProASIC FPGA

This paper presents the full-duplex architecture of the X-MatchPRO lossless datu compressor and its highly integrated implementation in a non-volatile reprogrammable ProASIC FPGA. The X-MatchPRO architecture ofsers a data independent throughput of 100 Mbytesh and simultaneous compression/decompression for a combine full-duplex performance of 200 Mbytesh clocking at 25 MHz. Both compression and decompression channels fit into a single A500K1.30 ProASIC FPGA with a typical compression ratio that halves the original uncompressed data. This device is specijically targeted to enhance the performance of Cbit/s data networks and storage applications where it can double the performance of the original system.