A 90 mW MPEG4 video codec LSI with the capability for core profile

Takashi Hashimoto,Shunichi Kuromaru,Masatoshi Matsuo, K Yasuo,Toshihiro Moriiwa,Kenichi Ishida,Shoji Kajita,Masatake Ohashi,Masayoshi Toujima,Tsuyoshi Nakamura,Masao Hamada,Takuro Yonezawa,Tetsuro Kondo, Kenta Hashimoto,Yuji Sugisawa,Hideki Otsuki,Masanori Arita,Hideo Nakajima,Hitoshi Fujimoto,Junji Michiyama,Yuichi Iizuka, Hitoshi Komori,Satoshi Nakatani,Hiroaki Toida, Toshiyuki Takahashi,Hideo Ito,Takeshi Yukitake

San Francisco, CA, USA（2001）

引用 43|浏览12

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摘要

A single-chip MPEG4 video codec LSI with 20 Mb embedded DRAM performs a QCIF 15 Hz H.263 codec, a Simple at L1 codec, and Core at L1 decoding. It consumes 90 mW at 54 MHz. This chip integrates a programmable DSP, 8 dedicated hardware engines, and interface units on a 75.68 mm/sup 2/ die using 0.18 /spl mu/m 1.8 V quad-metal CMOS technology.

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关键词

cmos digital integrated circuits,digital signal processing chips,large scale integration,video codecs,0.18 micron,1.8 v,54 mhz,90 mw,core at l1 decoding,h.263 codec,mpeg4,simple at l1 codec,core profile,dedicated hardware engines,embedded dram,interface units,programmable dsp,quad-metal cmos technology,video codec lsi,chip

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