Hot carrier reliability for 0.13 /spl mu/m CMOS technology with dual gate oxide thickness

Chuanzhe Lin,S Biesemans,L K Han,K Houlihan,T Schiml,K Schruefer,C Wann, Jhaoming Chen,R Mahnkopf

San Francisco, CA, USA（2000）

Cited 24|Views25

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Abstract

Different PMOS hot carrier degradation mechanisms are observed in a 0.13 /spl mu/m CMOS technology with ultra-thin gate oxide. Surprisingly, the gate voltage plays a significant role in total Idsat degradation, even at low temperature (40/spl deg/C). Hole trapping instead of electron trapping is observed under max Idsat degradation condition for PMOS. It is also shown that nitrogen affects NMOS and PMOS hot carrier degradation differently.

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Key words

cmos integrated circuits,electron traps,hole traps,hot carriers,integrated circuit reliability,0.13 micron,40 c,cmos technology,nmos device,pmos device,dual gate oxide thickness,electron trapping,hole trapping,hot carrier reliability,nitrogen implantation,saturation current,ultrathin gate oxide,nitrogen

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