Cost analysis of compliant wafer level package

Low cost package solutions are required by the semiconductor industry to meet the growing demand of high performance and high functionality in electronic products. In particular, the International Technology Roadmap for Semiconductors (ITRS) projects the package cost per pin to be as low as (0.30-1.26 cents) in 1999 to (0.27-0.93 cents) in 2005 to (0.24-0.68 cents) in 2011. To satisfy this need, a Compliant Wafer Level Package (CWLP) technology has been developed that: (a) packages all of the ICs intact on the wafer at once, and (b) fabricates all of the compliant Input/Output (I/O) connections monolithically in one step. Using discrete event simulations, a detailed manufacturing cost model for the CWLP is described. In contrast to the conventional packages where the cost of the package increases with the I/O count, the CWLP cost is independent of the I/O count because all of the I/Os are monolithically fabricated in one step. For 6-inch wafers and throughput greater than 50,000 wafers per year, the manufacturing cost of the CWLP is computed to be $26.65 per wafer. The percent contributions of the material, equipment and labor to the total cost is calculated to be 87%, 9%, and 4%, respectively