Mixed-signal CMOS wavelet compression imager architecture

The CMOS imager architecture implements ∆Σ- modulated block matrix transforms, such as Haar wavelet trans- form, on the focal plane, for real-time video compression. The active pixel array is integrated with a bank of column-parallel first-order incremental oversampling analog-to-digital converters (ADCs). Each ADC performs column-wise distributed focal-plane sampling and concurrent signed weighted average quantization, realizing a one-dimensional spatial filter. A digital delay and adder loop performs spatial accumulation over multiple adjacent ADC outputs. This amounts to computing a two-dimensional block matrix transform, with no overhead in time and negligent overhead in area compared to a baseline digital imager system. The architecture is experimentally validated on a 0.35 mi- cron CMOS prototype with a bank of first-order incremental oversampling ADCs computing Haar wavelet transform of an emulated pixel array output. The architecture yields simulated computational throughput of 1.4 GMACS with SVGA imager resolution at 30 frames per second.