Low-temperature metal/ON/HSG-cylinder capacitor process for high density embedded DRAMs
Kyoto, Japan（1999）
Abstract
A logic-process-compatible low-temperature hemispherical grain (HSG) cylinder capacitor process with maximum process temperature below 700/spl deg/C is developed. Depletion in HSG-grains and top-electrodes due to decreasing thermal budget is effectively suppressed by phosphorus doping with PH/sub 3/-annealing and the use of metal plate-electrodes. By combining with the HSG grain size optimization, the low-temperature process with highly reliable oxynitride (ON) dielectrics can be applied to high density embedded DRAM cells down to 0.13 /spl mu/m design rules.
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Key words
DRAM chips,annealing,capacitors,circuit optimisation,dielectric thin films,doping profiles,embedded systems,grain size,integrated circuit design,integrated circuit manufacture,integrated circuit reliability,0.13 micron,700 C,HSG grain size optimization,HSG-grain depletion,PH/sub 3/,PH/sub 3/-annealing,SiON,design rules,high density embedded DRAM cells,high density embedded DRAMs,logic-process-compatible low-temperature HSG cylinder capacitor process,low-temperature hemispherical grain cylinder capacitor process,low-temperature metal/ON/HSG-cylinder capacitor process,low-temperature process,metal plate-electrodes,phosphorus doping,process temperature,reliable oxynitride dielectrics,thermal budget,top-electrode depletion,
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