A MPEG4 programmable codec DSP with an embedded pre/post-processing engine

Kurohmaru, S.,Matsuo, M.,Nakajima, H.,Kohashi, Y.

San Diego, CA（1999）

引用 14|浏览2

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摘要

We have developed a programmable DSP for MPEG4, H.263, H.261 and wavelet based sub-band codec algorithms. This DSP has the capability of processing these algorithms in real-time and has excellent flexibility, so that it can, for instance, perform video codec at 15 CIF frames/sec or video/speech (G.723.1) codec at 30 QCIF frames/sec. This chip includes a video pre/post-processing engine and needs only one 16 Mbit SDRAM as an external memory to perform the above algorithms, making it possible to realize low-cost systems. This chip is fabricated using 0.25 um CMOS technology and contains 7.7 M transistors on 9.41 mm×9.22 mm die

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关键词

CMOS digital integrated circuits,digital signal processing chips,embedded systems,programmable circuits,video codecs,wavelet transforms,0.25 micron,CMOS DSP chip,MPEG4 programmable codec,SDRAM memory,embedded post-processing engine,embedded pre-processing engine,real-time processing,speech codec,video codec,wavelet subband algorithm,

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