Design rule driven behavioral synthesis for test
Signals, Systems & Computers, 1998. Conference Record of the Thirty-Second Asilomar Conference（1998）
摘要
We have developed a new approach to behavioral synthesis for testability. Utilizing a VHDL transformation environment, we have distilled design rules for testable VHDL generation. Design rules can be linked to specific design for test techniques, allowing simplified exploration of BIST, partial scan, and other test approaches. The result is a design methodology which is simple to use, improves testability, and decreases time to market.
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关键词
built-in self test,design for testability,hardware description languages,integrated circuit design,bist,vhdl transformation environment,design for test techniques,design methodology,partial scan,rule driven behavioral synthesis,testability,testable vhdl generation,time to market reduction,design rules,design for test
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