A 800Mb/s/pin 2GB DDR2 SDRAM using an 80nm triple metal technology

Kye Hyun Kyung,Chi Wook Kim,J Y Lee,Jeong Hoon Kook,Sung Min Seo,Du Yon Kim,Jun Hyung Kim,Jung Sunwoo, Hi Choon Lee,B H Jeong,Y S Sohn, S P Hong,J H Yoo,S I Cho

San Francisco, CA（2005）

Cited 6|Views16

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Abstract

A 1.8V, 800Mbit/s/pin, 2GB DDR2 SDRAM is developed using an 80nm triple metal technology. With the triple metal technology, NMOS precharge I/O scheme and statistical analysis, DDR800 4-4-4 performance is achieved at 1.8V. For mass production, a high-speed clock using an on chip PLL and an address-pin-reduction mode are employed.

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Key words

dram chips,mos integrated circuits,clocks,phase locked loops,statistical analysis,1.8 v,2 gb,80 nm,800 mbit/s,ddr2 sdram,ddr800 4-4-4 performance,nmos precharge i/o scheme,address-pin-reduction mode,high-speed clock,mass production,on chip pll,triple metal technology,chip

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