The Asynchronous 24MB On-Chip Level-3 Cache for a Dual-Core Itanium-family Processor
San Francisco, CA（2005）
Key words
asynchronous circuits,cache storage,delays,microprocessor chips,power consumption,0.8 V,24 MB,5-cycle array,85 degC,asynchronous level-3 cache,dual-core Itanium-family processor,on-chip level-3 cache,power saving,reduced latency,reliability improvement
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