A novel planarization technique for a high-T/sub c/ multilevel IC process

A novel technique has been developed to planarize insulating layers which may be used in a YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// (YBCO) IC process. The technique, called complementary mask planarization (CoMP), has been successfully implemented to planarize line gratings etched in an SrTiO/sub 3/ insulator. The average surface roughness of the line gratings as measured by an atomic force microscope (AFM) was reduced from 3000 to 250 /spl Aring/ after planarization. Films of YBCO were the posited and patterned in the form of narrow strips over the line gratings to simulate insulated crossovers in IC structures. The I-V characteristics of the YBCO strips over planarized line gratings showed that the critical current density is higher by two orders of magnitude than those over unplanarized gratings.